4 1 10 with an introduction to the verilog HDL MANO, M. MORRIS Primary Author CILETTI, MICHAEL D. Additional Author CHANDAVARKAR, B.R. Editor mixed material 9780273764526 Boston Pearson 2013 125729.jpg a constrain satisfaction approach for the architectural synthesis of digital VLSI circuits TIMMER, ADWIN H. Additional Author mixed material 9074445241 Eindhoven Universiteit Eindhoven 1996 HUIJBREGTS, EDUARD PETRUS Additional Author mixed material 9038601809 Eindhoven Technische Universiteit Eindhoven 1996 GAGELDONK, JOHAN SEBASTIAAN H.VAN Additional Author mixed material 907444542X Eindhoven Technische Universiteit Eindhoven 1998